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What happens to delay if you increase load capacitance? |
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How do you size NMOS and PMOS transistors to increase the threshold voltage? |
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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation |
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What is Noise Margin? Explain the procedure to determine Noise Margin |
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What happens if we use an Inverter instead of the Differential Sense Amplifier? |
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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width? |
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What would you do in order to not use certain cells from the library? |
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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance? |
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What is Body Effect? |
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What happens to delay if we include a resistance at the output of a CMOS circuit? |
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Draw a 6-T SRAM Cell and explain the Read and Write operations |
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Explain the various MOSFET Capacitances & their significance |
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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) |
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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times |
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What are the limitations in increasing the power supply to reduce delay? |
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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD |
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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) |
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Give the expression for calculating Delay in CMOS circuit |
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Describe the various effects of scaling |
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Give the expression for CMOS switching power dissipation |
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