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What are various techniques to resolve congestion/noise? |
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What would you do in order to not use certain cells from the library? |
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Why power stripes routed in the top metal layers? |
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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? |
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For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) |
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What’s the difference between Testing & Verification? |
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How can you model a SRAM at RTL Level? |
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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why? |
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Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers |
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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal? |
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What’s the critical path in a SRAM? |
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How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance? |
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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? |
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Draw the SRAM Write Circuitry |
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What happens if we use an Inverter instead of the Differential Sense Amplifier? |
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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation) |
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Draw a 6-T SRAM Cell and explain the Read and Write operations |
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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD |
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Why don’t we use just one NMOS or PMOS transistor as a transmission gate? |
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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram |
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