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VLSI Interview Questions & Answers

Below we have listed all the VLSI Interview Questions and answers. Feel free to comment on any VLSI Interview Questions or answer by the comment feature available on the page.

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How do you size NMOS and PMOS transistors to increase the threshold voltage?
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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
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What happens to delay if we include a resistance at the output of a CMOS circuit?
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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
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What happens to delay if you increase load capacitance?
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Give the expression for calculating Delay in CMOS circuit
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Explain why & how a MOSFET works
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Draw the stick diagram of a NOR gate. Optimize it
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Explain the various MOSFET Capacitances & their significance
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What is Noise Margin? Explain the procedure to determine Noise Margin
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Give the expression for CMOS switching power dissipation
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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
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Explain sizing of the inverter
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Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
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Why don?t we use just one NMOS or PMOS transistor as a transmission gate?
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In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
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How can you model a SRAM at RTL Level?
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