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VLSI Interview Questions & Answers

Below we have listed all the VLSI Interview Questions and answers. Feel free to comment on any VLSI Interview Questions or answer by the comment feature available on the page.

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VLSI Interview Questions & Answers

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. VLSI (very large-scale integration) is the current level of computer microchip miniaturization and refers to microchips containing in the hundreds of thousands of transistor s. LSI (large-scale integration) meant microchips containing thousands of transistors.

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How do you size NMOS and PMOS transistors to increase the threshold voltage?
4.4 Rating
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Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
4.1 Rating
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What happens to delay if we include a resistance at the output of a CMOS circuit?
3.7 Rating
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Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
4.7 Rating
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For CMOS logic, give the various techniques you know to minimize power consumption
4.8 Rating
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What are the limitations in increasing the power supply to reduce delay?
4.1 Rating
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What?s the critical path in a SRAM?
4.0 Rating
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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
3.1 Rating
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What are various techniques to resolve congestion/noise?
4.5 Rating
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Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
4.7 Rating
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What happens if we increase the number of contacts or via from one metal layer to the next?
3.8 Rating
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What would you do in order to not use certain cells from the library?
4.0 Rating
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What happens to delay if you increase load capacitance?
3.1 Rating
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Give the expression for calculating Delay in CMOS circuit
3.6 Rating
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Explain why & how a MOSFET works
3.6 Rating
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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
4.3 Rating
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Draw the stick diagram of a NOR gate. Optimize it
3.3 Rating
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What happens if we use an Inverter instead of the Differential Sense Amplifier?
3.7 Rating
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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
4.3 Rating
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Explain the various MOSFET Capacitances & their significance
3.5 Rating
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