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What is pipelining? |
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What are the five stages in a DLX pipeline? |
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For a pipeline with ‘n’ stages, what’s the ideal throughput? What prevents us from achieving this ideal throughput? |
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What are the different hazards? How do you avoid them? |
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Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages? |
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What are Branch Prediction and Branch Target Buffers? |
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How do you handle precise exceptions or interrupts? |
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What is a cache? |
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What’s the difference between Write-Through and Write-Back Caches? Explain advantages and disadvantages of each. |
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Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag. |
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What is Virtual Memory? |
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What is Cache Coherency? |
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What is a Snooping cache? |
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What are the components in a Microprocessor? |
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What is ACBF(Hex) divided by 16? |
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Convert 65(Hex) to Binary. |
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Convert a number to its two’s compliment and back |
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The CPU is busy but you want to stop and do some other task. How do you do it? |
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can u send me some questions on general computer concepts because i am preparing for keane software there they are asking questions on computers |
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what is the difference between interrupt service routine and subroutine ? |
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