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What is Static & Register variables? |
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For a pipeline with "n" stages, whats the ideal throughput? What prevents us from achieving this ideal throughput? |
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What is the difference between interrupt service routine and subroutine? |
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The CPU is busy but you want to stop and do some other task. How do you do it? |
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Convert a number to its twos compliment and back? |
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Convert 65(Hex) to Binary? |
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What is a cache? |
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What are the five stages in a DLX pipeline? |
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What is Virtual Memory? |
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What is Cache Coherency? |
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What is a Snooping cache? |
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Cache Size is 64KB, Block size is 32B and the cache is Two-Way Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag. |
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What is the pipelining? |
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What are the different hazards? How do you avoid them?
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What is MESI? |
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What are the basic components in a Microprocessor? |
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Can virtual memory be greater then main memory? |
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Can anyeone please let me explain (with ex) the 3 tiers and 5 tiers architecture? In BO 6.5 we used 3 tiers and BOXIR3 used 5 tiers.
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How many types of memory in computer architecture? |
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What is your Responsibilities in your project ?
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