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Question: Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Answer: The 5 stages of a DLX Pipeline are: IF - Instruction Fetch ID - Instuction Decode / Register Fetch EX - Execution / Effective Address Cycle MEM - Memory Access / Branch Completion Cycle WB - Write Back Assuming one clock per stage, it takes 5 clock cycles per instruction to get executed. Thus, latency = 5 Throughput - How often an insruction exits the pipeline defines the throughput ie, number of instructions completed / unit of time.
Submitted by Ramya Srinivasaraghavan ([email protected])
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Question:
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Answer:
The 5 stages of a DLX Pipeline are: IF - Instruction Fetch ID - Instuction Decode / Register Fetch EX - Execution / Effective Address Cycle MEM - Memory Access / Branch Completion Cycle WB - Write Back Assuming one clock per stage, it takes 5 clock cycles per instruction to get executed. Thus, latency = 5 Throughput - How often an insruction exits the pipeline defines the throughput ie, number of instructions completed / unit of time.
Submitted by Ramya Srinivasaraghavan ([email protected]) Source: CoolInterview.com
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