Hardware Design Interview Questions & Answers  Learning Mode  
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HARDWARE DESIGN INTERVIEW QUESTIONS QUESTIONS & ANSWERS  LEARNING MODE


Hardware Design Interview Questions & Answers  Learning ModeA Hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration. A computer hardware engineer is someone who researches, designs, develops, and tests computer equipment such as chips, circuit boards, or routers. 

Try Hardware Design Interview Questions & Answers  Exam Mode  
Hardware Design Interview Questions & Answers  Learning Mode 
Try Hardware Design Interview Questions & Answers  Exam Mode 
Question: What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Answer: Suppose your flipflop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint . Time for which data should be stable after the positive edge of clock is called as hold time constraint. if any of these constraints are violated then flipflop will enter in meta stable state, in which we cannot determine the output of flipflop. there are two equation: 1. Tcq + Tcomb> Tskew + Thold 2. Tcq + Tcomb< Source: CoolInterview.com 
Question: Give a circuit to divide frequency of clock cycle by two
Answer: You can divide the frequency of a clock by just implementing T Flip flop. Give clock as clock input and tie the T input to logic 1. Submitted by sanjum bhatia (sanjumbhatia4@yahoo.co.in) Source: CoolInterview.com 
Question: Give two ways of converting a two input NAND gate to an inverter.
Answer: One way is shorting the two inputs of the NAND gate and passing the input. truth table: A B output 1 1 0 0 0 1 The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one. truth table: A B output 1 1 0 0 1 1 Source: CoolInterview.com 
Question: Design a divideby3 sequential circuit with 50% duty circle.
Answer: Take a smiths counter with 3 f/f's that is to say with 6 states(2*3) now double the i/p clock frequency to the counter the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle so effectively u got divide by 3 freq with 50% duty cycle Source: CoolInterview.com 
Question: Give the truth table for a Half Adder. Give a gate level implementation of the same.
Answer: TRUTH TABLE FOR HALF ADDER: A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 IMPLEMENTATION: For SUM, The two inputs A and B are given to XOR gate. For Carry, The two inputs A and B are given to AND gate. Submitted by BOOTHI RAJ.P ( boothi.palanichamy@wipro.com) Source: CoolInterview.com 
Question: What are the different Adder circuits you studied?
Answer: Adders are generally of five types: 1) Ripple Carry Adder: The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA). These building blocks HAs and FAs are also the building blocks of all types of adders.The n full adders are cascaded to form n bit RCA. The full adder has three input pins(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1).Its equations are: Sum=Ai^Bi^Ci Ci+1=Ai.Bi+Bi.Ci+Ai.CiCoolInterview.com 
Question: Explain the working of a binary counter.
Answer: 
Question: How do you detect if two 8bit signals are same?
Answer: XOR each bits of A with B (for eg A[0] xor B[0] ) and so on. the o/p of 8 xor gates are then given as i/p to an 8i/p nor gate. if o/p is 1 then A=B. Source: CoolInterview.com 
Question: Given a circuit, draw its exact timing response.
Answer: 
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