Hardware Design Interview Questions & Answers  Learning Mode  
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HARDWARE DESIGN INTERVIEW QUESTIONS QUESTIONS & ANSWERS  LEARNING MODE


Hardware Design Interview Questions & Answers  Learning ModeA Hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration. A computer hardware engineer is someone who researches, designs, develops, and tests computer equipment such as chips, circuit boards, or routers. 

Try Hardware Design Interview Questions & Answers  Exam Mode  
Hardware Design Interview Questions & Answers  Learning Mode 
Try Hardware Design Interview Questions & Answers  Exam Mode 
Question: Design any FSM in VHDL or Verilog.
Answer: 
Question: Give two ways of converting a two input NAND gate to an inverter.
Answer: Short the two inputs of the nand gate and give the same input to the common wire,the nand gate works as an inverter. Submitted by MOHAMMAD USAID ABBASI (usaidabbasi@yahoo.com) ___________ One way is shorting the two inputs of the NAND gate and passing the input. truth table: A B output 1 1 0 Source: CoolInterview.com 
Question: Draw a Transmission Gatebased DLatch.
Answer: 
Question: Design a divideby3 sequential circuit with 50% duty circle.
Answer: 
Question: How do you detect a sequence of "1101" arriving serially from a signal line?
Answer: Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero. Ex : if the given sequence to be detected is 111 and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1. Soln: One of the different possible ways to detect a sequence is using a Mealy type FSM. Using the following table the State machine can be designed. since the number of bits in the sequence 110 Source: CoolInterview.com 
Question: What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Answer: Setup time is the minimum time prior to trigerring edge of the clock pulse upto which the data should be kept stable at the flipflop input so that data could be properly sensed at the input.Hold time is the minimum time after the clock edge upto which the data should be kept stable in order to trigger the flip flop at right voltage level. Setup time is required in order to find the maximum clock frequency of a circuit. Submitted by MOHAMMAD USAID ABBASI (usaidabbasi@yahoo.com) __ Source: CoolInterview.com 
Question: Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
Answer: 
Question: Give a circuit to divide frequency of clock cycle by two
Answer: You can divide the frequency of a clock by just implementing T Flip flop. Give clock as clock input and tie the T input to logic 1. Submitted by sanjum bhatia (sanjumbhatia4@yahoo.co.in) Source: CoolInterview.com 
Question: Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can?t resize the combinational circuit transistors)
Answer: 
Question: What are the different Adder circuits you studied?
Answer: Adders are generally of five types: 1) Ripple Carry Adder: The Ripple carry adder(RCA) consists of a building block named Half Adder(HA) which is cascaded to form a Full Adder(FA). These building blocks HAs and FAs are also the building blocks of all types of adders.The n full adders are cascaded to form n bit RCA. The full adder has three input pins(input Ai,input Bi,carryin Ci) and two output pins(Sum and Ci+1).Its equations are: Sum=Ai^Bi^Ci Ci+1=Ai.Bi+Bi Source: CoolInterview.com 
Question: What is the difference between SYNONYM and ALIAS?
Answer: Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero. Ex : if the given sequence to be detected is 111 and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1. Soln: One of the different possible ways to detect a sequence is using a Mealy type FSM. Using the following table the State machine can be designed. since the number of bits in the sequence 1101 is Source: CoolInterview.com 
Question: Explain RC circuit?s charging and discharging.
Answer: 
Question: Give the truth table for a Half Adder. Give a gate level implementation of the same.
Answer: TRUTH TABLE FOR HALF ADDER: A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 IMPLEMENTATION: For SUM, The two inputs A and B are given to XOR gate. For Carry, The two inputs A and B are given to AND gate. Submitted by BOOTHI RAJ.P ( boothi.palanichamy@wipro.com) Source: CoolInterview.com 
Question: Give the truth table for a Half Adder. Give a gate level implementation of the same.
Answer: TRUTH TABLE FOR HALF ADDER: A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 IMPLEMENTATION: For SUM, The two inputs A and B are given to XOR gate. For Carry, The two inputs A and B are given to AND gate. Source: CoolInterview.com 
Question: Explain RC circuit?s charging and discharging.
Answer: 
Question: Give a circuit to divide frequency of clock cycle by two?
Answer: You can divide the frequency of a clock by just implementing T Flip flop. Give clock as clock input and tie the T input to logic 1. Source: CoolInterview.com 
Question: Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal?
Answer: Use the concept of registerretiming. divide the total combinatorial delay in two segments such that individually the delay is less the clock period. this can be done by inserting a flipflop in the combinational path. e.g, clock period  5 ns total cominational delay  7 then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flipflop in between. Source: CoolInterview.com 
Question: What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Answer: Suppose your flipflop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint . Time for which data should be stable after the positive edge of clock is called as hold time constraint. if any of these constraints are violated then flipflop will enter in meta stable state, in which we cannot determine the output of flipflop. there are two equation: 1. Tcq + Tcomb> Tskew + Thold 2. Tcq + Tcomb< Source: CoolInterview.com 
Question: How do you detect if two 8bit signals are same?
Answer: XOR each bits of A with B (for eg A[0] xor B[0] ) and so on. the o/p of 8 xor gates are then given as i/p to an 8i/p nor gate. if o/p is 1 then A=B. Submitted by Sreeni Somakumar (sreeni_somakumar@yahoo.co.in) Source: CoolInterview.com 
Question: Give two ways of converting a two input NAND gate to an inverter.
Answer: One way is shorting the two inputs of the NAND gate and passing the input. truth table: A B output 1 1 0 0 0 1 The second way is passing the input to only one input(say A) of the NAND gate.Since the other input(say B) is floating, it is always logic one. truth table: A B output 1 1 0 0 1 1 Source: CoolInterview.com 
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