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Intel Interview Questions & Answers - Learning Mode
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Intel Interview Questions & Answers - Learning Mode

Intel Corporation is an American multinational technology company headquartered in Santa Clara, California. Intel is one of the world's largest and highest valued semiconductor chip makers, based on revenue. It is the inventor of the x86 series of microprocessors, the processors found in most personal computers. Intel supplies processors for computer system manufacturers such as Apple, Samsung, HP and Dell.

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Intel Interview Questions & Answers - Learning Mode
Try Intel Interview Questions & Answers - Exam Mode
Question: In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

Answer: If the signal coming to the to the synchronous state machine is generated in different clock domain than the state machine clock. This avoids the metastability of the coming signal.

Submitted by Raja sekhar Kalapati (raja_asic@yahoo.com) Source: CoolInterview.com
Question: Explain the difference between write through and write back cache.

Answer: A type of cache with the following feature: when changes are made to cached data, they are not simultaneously made to the original data as well. Instead, the changed data is marked, and the original data is updated when the chached data is deallocated. In a write-through cache, by contrast changes made to cached data are simultaneously made in the original copy. A write-back cache can perform more quickly than a write-through cache. But in some contexts, differences between cached and original d Source: CoolInterview.com
Question: Are you familiar with VHDL and/or Verilog?

Answer:
Question: Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?

Answer: The 5 stages of a DLX Pipeline are:
IF - Instruction Fetch
ID - Instuction Decode / Register Fetch
EX - Execution / Effective Address Cycle
MEM - Memory Access / Branch Completion Cycle
WB - Write Back

Assuming one clock per stage, it takes 5 clock cycles per instruction to get executed. Thus, latency = 5

Throughput - How often an insruction exits the pipeline defines the throughput ie, number of instructions completed / unit of time.


Submitted b Source: CoolInterview.com
Question: What was your role in the silicon evaluation/product ramp? What tools did you use?

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Question: Are you familiar with the term snooping?

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Question: What transistor level design tools are you proficient with? What types of designs were they used on?

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Question: What types of high speed CMOS circuits have you designed?

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Question: What are the total number of lines written by you in C/C++? What is the most complicated/valuable program written in C/C++?

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Question: What are the main issues associated with multiprocessor caches and how might you solve them?

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Question: Have you studied buses? What types?

Answer: There are three types of buses.

1. Address bus: This is used to carry the Address to the memory to fetch either Instruction or Data.

2 .Data bus : This is used to carry the Data from the memory.

3. Control bus : This is used to carry the Control signals like RD/WR, Select etc.

Submitted by Boothi Raj.P (bothees@gmail.com)




Source: CoolInterview.com
Question: How many bit combinations are there in a byte?

Answer: Byte contains 8 combinations of bits. Source: CoolInterview.com
Question: What types of CMOS memories have you designed? What were their size? Speed?

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Question: What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

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Question: What compiler was used?

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Question: You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

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Question: Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

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Question: Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

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Question: If not into production, how far did you follow the design and why did not you see it into production?

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Question: For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

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Latest 20 Questions
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