when a suitable polarity potential is applied at gate a conducting channel will form. This conducting channel can be used for switching or amplification
Posted by: san
MOSFET is a metal oxide semiconductor Field effect transistor, its unidirectional device like, formed by four terminals GATE,SOURCE,DRAIN AND SUSTRATE. GATE is the control signal, depends upon voltage applied at gate terminal MOSFET work on three regions saturation, cutoff and active region. active region is used for amplification, cut-off and saturation region used for switching operation, mostly digital ckt design
Posted by: srilatha
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Two power MOSFETs in the surface-mount package D2PAK. Operating as switches, each of these components can sustain a blocking voltage of 120 volts in the OFF state, and can conduct a continuous current of 30 amperes in the ON state, dissipating up to about 100 watts and controlling a load of over 2000 watts. A matchstick is pictured for scale.
A cross section through an nMOSFET when the gate voltage VGS is below the threshold for making a conductive channel; there is little or no conduction between the terminals source and drain; the switch is off. When the gate is more positive, it attracts electrons, inducing an n-type conductive channel in the substrate below the oxide, which allows electrons to flow between the n-doped terminals; the switch is on.
Simulation result for formation of inversion channel (electron density) and attainment of threshold voltage (IV) in a nanowire MOSFET. Note that the threshold voltage for this device lies around 0.45V.
The metal?oxide?semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a device used for amplifying or switching electronic signals. The basic principle of the device was first proposed by Julius Edgar Lilienfeld in 1925. In MOSFETs, a voltage on the oxide-insulated gate electrode can induce a conducting channel between the two other contacts called source and drain. The channel can be of n-type or p-type (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOS, pMOS). It is by far the most common transistor in both digital and analog circuits, though the bipolar junction transistor was at one time much more common.
The 'metal' in the name is now often a misnomer because the previously metal gate material is now often a layer of polysilicon (polycrystalline silicon). Aluminium had been the gate material until the mid 1970s, when polysilicon became dominant, due to its capability to form self-aligned gates. Metallic gates are regaining popularity, since it is difficult to increase the speed of operation of transistors without metal gates.
IGFET is a related term meaning insulated-gate field-effect transistor, and is almost synonymous with MOSFET, though it can refer to FETs with a gate insulator that is not oxide. Another synonym is MISFET for metal?insulator?semiconductor FET.
* 1 Composition
* 2 Circuit symbols
* 3 MOSFET operation
o 3.1 Metal?oxide?semiconductor structure
o 3.2 MOSFET structure and channel formation
o 3.3 Modes of operation
o 3.4 Body effect
* 4 The primacy of MOSFETs
* 5 CMOS circuits
o 5.1 Digital
o 5.2 Analog
* 6 MOSFET scaling
o 6.1 Reasons for MOSFET scaling
o 6.2 Difficulties arising due to MOSFET size reduction
+ 6.2.1 Higher subthreshold conduction
+ 6.2.2 Increased gate-oxide leakage
+ 6.2.3 Increased junction leakage
+ 6.2.4 Lower output resistance
+ 6.2.5 Lower transconductance
+ 6.2.6 Interconnect capacitance
+ 6.2.7 Heat production
+ 6.2.8 Process variations
+ 6.2.9 Modeling challenges
* 7 MOSFET construction
o 7.1 Gate material
o 7.2 Insulator
o 7.3 Junction design
* 8 Other MOSFET types
o 8.1 Dual gate MOSFET
+ 8.1.1 FinFET
o 8.2 Depletion-mode MOSFETs
o 8.3 NMOS logic
o 8.4 Power MOSFET
o 8.5 DMOS
o 8.6 RHBD MOSFETs
* 9 MOSFET analog switch
o 9.1 Single-type MOSFET switch
o 9.2 Dual-type (CMOS) MOSFET switch
* 10 References and notes
* 11 See also
* 12 External links
Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two gates and three source/drain nodes are labeled.
Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, recently started using a compound (mixture) of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good semiconductor-to-insulator interfaces, thus are not suitable for MOSFETs. Research continues on creating insulators with acceptable electrical characteristics on other semiconductor material.
In order to overcome power consumption increase due to gate current leakage, high-κ dielectric replaces silicon dioxide for the gate insulator, while metal gates return by replacing polysilicon (see Intel announcement).
The gate is separated from the channel by a thin insulating layer, traditionally of silicon dioxide and later of silicon oxynitride. Some companies have started to introduce a high-κ dielectric + metal gate combination in the 45 nanometer node.
When a voltage is applied between the gate and body terminals, the electric field generated penetrates through the oxide and creates an alleged "inversion layer" or "channel" at the semiconductor-insulator interface. The inversion channel is of the same type, P-type or N-type, as the source and drain, thus it provides a channel through which current can pass. Varying the voltage between the gate and body modulates the conductivity of this layer and allows to control the current flow between drain and source.
 Circuit symbols
A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for enhancement mode and a solid line for depletion mode. Another line is drawn parallel to the channel for the gate.
The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in (from the bulk to the channel). If the bulk is connected to the source (as is generally the case with discrete devices) it is sometimes angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS, alternatively an arrow on the source may be used in the same way as for bipolar transistors (out for NMOS, in for PMOS).
Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols (drawn with source and drain ordered such that higher voltages appear higher on the page than lower voltages):
JFET P-Channel Labelled.svg IGFET P-Ch Enh Labelled.svg IGFET P-Ch Enh Labelled simplified.svg Mosfet P-Ch Sedra.svg IGFET P-Ch Dep Labelled.svg P-channel
JFET N-Channel Labelled.svg IGFET N-Ch Enh Labelled.svg IGFET N-Ch Enh Labelled simplified.svg Mosfet N-Ch Sedra.svg IGFET N-Ch Dep Labelled.svg N-channel
JFET MOSFET enh MOSFET enh (no bulk) MOSFET dep
For the symbols in which the bulk, or body, terminal is shown, it is here shown internally connected to the source. This is a typical configuration, but by no means the only important configuration. In general, the MOSFET is a four-terminal device, and in integrated circuits many of the MOSFETs share a body connection, not necessarily connected to the source terminals of all the transistors.
Example application of an N-Channel MOSFET. When the switch is pushed the LED lights up.
Metal?oxide?semiconductor structure on P-type silicon
 Metal?oxide?semiconductor structure
A traditional metal?oxide?semiconductor (MOS) structure is obtained by growing a layer of silicon dioxide (SiO2) on top of a silicon substrate and depositing a layer of metal or polycrystalline silicon (the latter is commonly used). As the silicon dioxide is a dielectric material, its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.
When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with NA the density of acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage, VGB, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions (see doping (semiconductor)). If VGB is high enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. Unlike the MOSFET, where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region. Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage.
This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.
 MOSFET structure and channel formation
Cross section of an NMOS without channel formed: OFF state
Cross section of an NMOS with channel formed: ON state
A metal?oxide?semiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to as oxide) are employed the device may be referred to as a metal?insulator?semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a '+' sign after the type of doping.
If the MOSFET is an n-channel or nMOS FET, then the source and drain are 'n+' regions and the body is a 'p' region. As described above, with sufficient gate voltage, above a threshold voltage value, electrons from the source (and possibly also the drain) enter the inversion layer or n-channel at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between source and drain.
For gate voltages below the threshold value, the channel is lightly populated, and only a very small subthreshold leakage current can flow between the source and the drain.
If the MOSFET is a p-channel or pMOS FET, then the source and drain are 'p+' regions and the body is a 'n' region. When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for p-channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain.
The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.
The device may comprise a Silicon On Insulator (SOI) device in which a Buried OXide (BOX) is formed below a thin semiconductor layer. If the channel region between the gate dielectric and a Buried OXide (BOX) region is very thin, the very thin channel region is referred to as an Ultra Thin Channel (UTC) region with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. Alternatively, the device may comprise a SEMiconductor On Insulator (SEMOI) device in which other semiconductors than silicon are employed. Many alternative semicondutor materials may be employed.
When the source and drain regions are formed above the channel in whole or in part, they are referred to as Raised Source/Drain (RSD) regions.
Posted by: cherry
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