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Question: What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

Answer: Setup time is the minimum time prior to trigerring edge of the clock pulse upto which the data should be kept stable at the flip-flop input so that data could be properly sensed at the input.Hold time is the minimum time after the clock edge upto which the data should be kept stable in order to trigger the flip flop at right voltage level. Setup time is required in order to find the maximum clock frequency of a circuit.

Submitted by MOHAMMAD USAID ABBASI (usaidabbasi@yahoo.com)

___________

Setup time :It is the minimum time before the clock edge the input should be stable.This is due to the input capacitance present at the input.It takes some time to charge to the particular logic level at the input.

Hold time:It is the minimum time the input should be present stable after the clock edge.This is the time taken for the various switching elements to transit from saturation to cut off and vice versa.

So basically set up and hold time is the window during which the input should be stable.Any changes in the input during the window period may lead to voltage levels which is not recognised by the subsequent stages and the circuit may go to metastable stage.

Submitted by Thomas Varghese (tomcrux@fastmail.fm)

______

suppose ur flip-flop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint .

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:
1. Tcq + Tcomb> Tskew + Thold
2. Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time delay when data enters the flip-flop and data comes at output of flip flop.
Tcomb is the logic delay between two flip flop.
Tskew is the delay of clock to flip flop: suppose there are two flip flop ,if clock reaches first to source flip flop and then after some delay to destination flip flop ,it is positive skew and if vice versa then negative skew.

so if u take 2 eq you will see that setup time is the determining factor of clock's time period.

Submitted by Sanjum Bhatia (sanjumbhatia4@yahoo.co.in)



Category Hardware Design Interview Questions & Answers - Exam Mode / Learning Mode
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Question: What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
Answer:

Setup time is the minimum time prior to trigerring edge of the clock pulse upto which the data should be kept stable at the flip-flop input so that data could be properly sensed at the input.Hold time is the minimum time after the clock edge upto which the data should be kept stable in order to trigger the flip flop at right voltage level. Setup time is required in order to find the maximum clock frequency of a circuit.

Submitted by MOHAMMAD USAID ABBASI (usaidabbasi@yahoo.com)

___________

Setup time :It is the minimum time before the clock edge the input should be stable.This is due to the input capacitance present at the input.It takes some time to charge to the particular logic level at the input.

Hold time:It is the minimum time the input should be present stable after the clock edge.This is the time taken for the various switching elements to transit from saturation to cut off and vice versa.

So basically set up and hold time is the window during which the input should be stable.Any changes in the input during the window period may lead to voltage levels which is not recognised by the subsequent stages and the circuit may go to metastable stage.

Submitted by Thomas Varghese (tomcrux@fastmail.fm)

______

suppose ur flip-flop is positive edge triggered. time for which data should be stable prior to positive edge clock is called setup time constraint .

Time for which data should be stable after the positive edge of clock is called as hold time constraint.

if any of these constraints are violated then flip-flop will enter in meta stable state, in which we cannot determine the output of flip-flop.

there are two equation:
1. Tcq + Tcomb> Tskew + Thold
2. Tcq + Tcomb<Tskew +T - Tsetup

Tcq is time delay when data enters the flip-flop and data comes at output of flip flop.
Tcomb is the logic delay between two flip flop.
Tskew is the delay of clock to flip flop: suppose there are two flip flop ,if clock reaches first to source flip flop and then after some delay to destination flip flop ,it is positive skew and if vice versa then negative skew.

so if u take 2 eq you will see that setup time is the determining factor of clock's time period.

Submitted by Sanjum Bhatia (sanjumbhatia4@yahoo.co.in) Source: CoolInterview.com



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